1. Field of the Invention
The invention relates to design methodologies for electrical systems, more in particular electrical circuits (especially digital circuits), to circuitry designed with said methodologies and to circuit parts, specially designed and incorporated within said digital circuits to enable operation of said circuits in accordance with the proposed concepts.
2. Description of the Related Art
Technology scaling has historically improved the performance of embedded systems, both in energy consumption and in speed. Scaling minimum feature sizes below 100 nm however, brings a host of problems, which cannot be completely solved at technology level. Back-end performance degradation and increased leakage currents are only a few examples. It is know in the art that future deep submicron (DSM) technologies will suffer more and more from leakage problems. Such leakage problems are temperature an/or ageing dependent.
Currently available thermal management of platforms already react on too high temperatures for certain modules but they try to remedy the situation when it has become “critical”. So if the temperature within the modules reaches a too high value, they shut off the module and move the operations to other spare modules.
Leakage in future technology nodes is assumed to be dominated by gate and subthreshold leakage. The gate leakage can be kept under control by not reducing the oxide thickness too much and by using high-k materials. So technology innovations should keep that contribution low up till at least 45 nm. The subthreshold leakage, however, is not solvable by technology innovations. For the subthreshold leakage, either the threshold voltage Vt has to be kept high enough, or the temperature low enough (because subthreshold leakage rises exponentially with reducing threshold voltage). Keeping the threshold voltage Vt high means a significant penalty on delay, especially if the supply voltage Vdd is low enough to keep also the dynamic power low in future technology nodes.
Due to the stochastic nature of leakage caused by temperature variations and/or ageing, the only way to maximize the parametric system yield, i.e. the number of samples that meet the timing constraints, is either by incorporating corner-point analysis in the designs, or by run-time techniques which can measure the actual variability and adapt the operation of the system, because it is impossible to predict the impact of leakage caused by temperature variations and/or ageing on a system before the chip is processed, in particular in view of the temperature-dependence.
Especially deep submicron (DSM) technologies, e.g. process technology nodes for 65 nm and beyond, suffer from large variability in integrated circuit (IC) parameters. These variations may be due to, amongst others, the following reasons:                “temporal” differences due to “degradation” processes, i.e. ageing. These include electromigration (which influences resistance R and partly capacitance C of lines), self-annealing of Cu (which influences resistance R of lines), stability of low-k dielectrics (which influences R/C of lines) and of high-k dielectrics (which influences threshold voltage Vt), hot electron trapping (which also influences threshold voltage Vt) and cross-talk (which causes “pseudo C” changes and noise). These temporal differences should be relatively slow and easy to “follow up” or monitor.        “temperature-related” differences due to strong variations in temperature T over time. Because of this, threshold voltage Vt and resistance R of lines are influenced. These temperature-related differences can vary quite fast (up to msec range) and hence are more difficult to monitor and calibrate.        
Memories are among the most leakage sensitive components of a system. The reason is that most of the transistors in a memory are minimum-sized and are thus more prone to leakage caused by temperature variations and ageing. Additionally some parts of the memories are analog blocks, whose operation and timing can be severely degraded by leakage caused by temperature variations and ageing.
In a target domain of multimedia applications, memories occupy the majority of the chip area even in current designs and contribute to the majority of the digital chip energy consumption. Therefore they are considered to be very important blocks for a system.
Leakage caused by temperature variations and ageing have thus become a serious problem for continued technology scaling. It becomes harder and harder to deal with this at the technology and circuit levels only. Several proposed schemes are not even scalable to deep-submicron technologies because the body-bias effect will become very small.
If these effects have to be characterized at “design time”, and furthermore it has to be guaranteed that the design will still work under all possible conditions, in particular temperature conditions, the slack that will have to be introduced will become prohibitive in the deep-submicron era.
Maximizing parametric yield in memories via corner-point analysis and design will, by the size of the “clouds” due to leakage caused by temperature variations and ageing, lead to severe overheads in energy consumption and delay. The reason is that the memory design will use over-sized circuits and conservative timing margins to improve the predictability of the memory behavior by trading off performance.